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Popular News
Daily News
Total : 255 ( 8/26 Pages)
SDI II IP Step by Step Implementation Guide for an Altera Arria 10 Device
by Altera - 2014-11-14 17:02 - 59,789 views
This video demonstrates how to implement an Altera SDI II IP core in an Arria 10 device. In the beginning, you will see a high level diagram of a complete SDI II IP design architecture together with some explanation on the differences from previous device families. Finally, you will be guided through step by step generation in Quartus II software for all necessary transceiver related components and integration.
Implement Transceiver Design Using Qsys and Transceiver Toolkit in Quartus II Software
by Altera - 2014-11-13 17:41 - 4,405 views
- Implementing a Cyclone V GX 2G transceiver design using the TerASIC Cyclone V GX development kit - Show kit, point to example LPDDR2 design, show top level RTL, Qsys system integration tool qsf file, Quartus II software compile, download sof - Bring up transceiver toolkit, set serial loopack and verify error free operation - Connect HSMC loopback board and verify error free operation
Power Management For FPGA Users: Core Power Requirements
by Altera - 2014-11-11 16:05 - 3,570 views
Watch this short in-lab video to get an inside look into FPGA core rail power requirements and how to meet them. Learn more: http://www.altera.com/power-resource-...
Implementing a Partial Reconfiguration Design within Qsys for Altera FPGAs
by Altera - 2014-10-21 15:20 - 137,359 views
Partial Reconfiguration enables you to dynamically reconfigure a portion of the FPGA while the rest of the design remains fully operational. Qsys is a system integration tool within the Quartus II software.
From Qsys to Quartus
by Altera - 2014-10-21 15:02 - 7,284 views
This video walks through the creation of a system in Qsys, what files are generated, how to pull those files into Quartus, advantages/disadvantages of various design flows (.qip –vs .qsys, qsys as the top level –vs- as a design block), and timing constraints for an Altera FPGA
Configuring HPS to FPGA and FPGA to HPS Bridges in Altera SoCs
by Altera - 2014-10-21 15:01 - 7,596 views
- How to configure the AXI bridges from HPS (Hard Processor System) MegaWizard with a simple design - Learn the characteristics and application of each bridge – HPS-FPGA bridge, Lightweight HPS-FPGA bridge, FPGA-HPS bridge - Learn how to achieve optimization in Qsys with selection of bridges in different application
JTAG external trace on Altera SoCs using DSTREAM
by Altera - 2014-10-21 14:48 - 8,271 views
- Brief introduction to Altera SoC, board & SoC EDS, tracing - Step-by-step demonstration on how to trace bare-metal program
Getting Started with the Quartus II New Project Wizard
by Altera - 2014-10-21 14:48 - 6,603 views
This video is a basic walkthrough on how to use the New Project Wizard in the Quartus II Software to quickly start creating an Altera FPGA design.
JTAG External Trace on Altera SoCs Using Lauterbach
by Altera - 2014-10-21 11:50 - 8,238 views
- Brief introduction to Altera SoC, board & Lauterbach tracing - Step-by-step demonstration on how to debug & trace bare-metal program with Lauterbach
次世代不揮発性 FPGA 新登場
by Altera - 2014-10-21 11:41 - 4,628 views
MAX 10 FPGAの詳細: http://www.altera.co.jp/max10 アルテラの 55nm MAX 10 FPGA は、外部システム・コンポーネント機能をより多く集積したことにより、 システム・レベ­ルでのコスト削減を実現します。CPLD とは異なり、デジタル信号処理 (DSP) ブロック、 アナログ-デジタル・コンバータ (ADC) および温度センサを搭載したアナログ・ブロック、エンベデッド・ ソフト・プロセッサの­サポート、メモリ・コントローラ、デュアル・コンフィギュレーション・フラッシュ・ メ­モリといった、フル装備の FPGA機能を備えています。

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