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Popular News
Daily News
Total : 255 ( 7/26 Pages)
Migration from legacy 10G Ethernet MAC IP to the new low latency 10G Ethernet MAC IP
by Altera - 2014-12-18 16:28 - 7,089 views
This video introduces the Altera Low Latency 10G Ethernet MAC IP Core and demonstrates the migration steps from the legacy 10G Ethernet MAC IP core. This could be helpful especially for those who plan to port over an existing design to the Arria 10 device family (exclusively supported by Low Latency 10G Ethernet MAC IP Core).
Scalable 10G MAC + 1G/10G PHY with 1588 Design Example Hardware Demo
by Altera - 2014-12-18 16:28 - 7,804 views
The scalable design serves as a good example and reference to show Altera 10G Ethernet MAC IP and 1G/10G PHY IP with IEEE 1588 feature. Learn how to perform the design hardware test and also how to modify the hardware tcl script to specify test purpose.
Board Timing For Arria 10 EMIF IP
by Altera - 2014-12-18 16:27 - 9,028 views
The purpose of this video is to show briefly how to fill up the board timing tab, explain Altera external memory interface (EMIF) simulation guidance and introduce the collateral available for more information
How to Migrate Altera Triple Speed Ethernet to Arria 10 Devices in Quartus II Software v. 14.0
by Altera - 2014-12-18 15:32 - 3,692 views
Arria 10 FPGAs are part of a new Altera device generation which delivers higher performance than previous-generation high-end FPGAs while simultaneously reducing power by offering a comprehensive set of power-saving technologies. Hence, it is essential to migrate all IP cores including Triple Speed Ethernet IP from older devices to Arria 10 devices.
How to Debug Altera Triple Speed Ethernet Link Synchronization Issue
by Altera - 2014-12-18 15:29 - 4,142 views
The very first thing to bring up the Ethernet design successfully is to make sure the link synchronization is up before starting any transmit or receive packets activities. Hence, how to resolve the link synchronization issue becomes vital for Ethernet in general and Triple Speed Ethernet in specific.
How to Debug Altera Triple Speed Ethernet Auto Negotiation Issue
by Altera - 2014-12-18 15:26 - 4,100 views
Two different devices cannot communicate successfully if they are operating in different speed and duplex. In order for them to share the same speed and duplex, auto negotiation is essential. In consequence, debugging auto negotiation issue becomes vital for Ethernet in general and Triple Speed Ethernet in specific.
Quick Signal Tapping with SignalProbe in the Altera Quartus II Software
by Altera - 2014-12-18 15:20 - 3,053 views
See how to quickly bring internal FPGA design signals out to unused I/O pins for debugging using SignalProbe!
How to Use the Altera Board Skew Parameter Tool
by Altera - 2014-11-27 14:16 - 4,788 views
This video will demonstrate how to use the Board Skew Parameter Tool to assist in calculating board skew parameters needed when generating an Altera® external memory interface IP
Getting Started with the TimeQuest Timing Analyzer
by Altera - 2014-11-27 14:09 - 51,893 views
Learn the basics of setting up and generating timing reports with the TimeQuest Timing Analyzer within the Altera Quartus II software
Creating Custom Qsys Components with the Qsys Component Editor
by Altera - 2014-11-27 14:08 - 4,343 views
Learn how to use the Component Editor to turn a custom HDL design into a Qsys-compatible system component

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