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Popular News
Daily News
Total : 255 ( 2/26 Pages)
Altera Mini Delta Robot (Cyclone V SoC based)
by Altera - 2015-02-02 15:26 - 5,647 views
Altera Cyclone V SoC based single-chip motion control unit with EtherCAT master accelerates simultaneous control of multi-axis servo drives, over Altera Cyclone IV based EtherCAT slave interfaces. Altera Cyclone III manages Encoder Interface.
How to Measure TX Jitter for PRBS23 at 10.3125Gbps Using Lecroy RTS
by Altera - 2015-01-19 17:05 - 5,733 views
This video shows how to measure TX jitter for a PRBS23 data pattern at 10.3125Gbps using a Lecroy Real Time Scope (RTS). The video shows how to set up the RTS to measure a long data pattern and how to decompose jitter and measure accurate TJ, RJ, and DJ components for PRBS23.
Introduction to JNEye (Jitter/Noise Eye Link Analysis Tool)
by Altera - 2015-01-19 17:04 - 5,463 views
Learn how the Altera JNEye tool provides a highly-optimized tool flow for link analysis.
How to Generate Arria 10 EMIF Example Design
by Altera - 2015-01-19 16:11 - 6,721 views
This video demonstrates how to generate an Altera Arria 10 FPGA EMIF (external memory interface) example design using the Quartus II software v. 14.1. It shows how to fill in the Parameter Editor General Tab.
MAX 10 FPGA - Booting Nios II Processor (Part 2)
by Altera - 2015-01-19 16:10 - 6,081 views
This video demonstrates how to boot an Altera Nios II processor from a MAX 10 FPGA with different configuration methods. This Part 2 video shows how the boot copier copies Nios II application from Altera on-chip Flash to OCR/External RAM and also demonstrates MAX 10 Nios II dual boot configuration.
MAX 10 FPGA – Booting Nios II Processor (Part 1)
by Altera - 2015-01-19 16:08 - 5,462 views
This video demonstrates booting a Nios II processor from a MAX 10 FPGA with different configuration methods. This Part 1 video shows how to boot a Nios II processor from Altera On Chip RAM and Nios II execute-in-place from Altera On Chip Flash.
Tips to Implement Transceiver Dynamic Reconfiguration in 28-nm Devices
by Altera - 2015-01-19 16:08 - 5,208 views
This video shows you how to implement different transceiver dynamic reconfiguration features in 28-nm devices. The reference design used in this video can be downloaded from the Altera Wiki page.
Introduction to JNEye (Jitter/Noise Eye Link Analysis Tool)
by Altera - 2014-12-31 11:12 - 10,353 views
Learn how the Altera JNEye tool provides a highly-optimized tool flow for link analysis.
Voltage Sensor in Arria 10 Devices
by Altera - 2014-12-31 11:11 - 22,377 views
This video shows you how to configure and use the voltage sensor in Altera Arria 10 devices.
SignalTap II Embedded Logic Analyzer Basics
by Altera - 2014-12-31 11:11 - 13,184 views
See how to set up and perform a basic Altera FPGA functional design analysis with the SignalTap II embedded logic analyzer within the Quartus II software!

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